Attempts continue to shrink the dimensions for fabricating MOS transistors. Devices having sub-micrometer dimensions permit closer placement of devices, thereby increasing the density of devices on a chip and also increasing device operating speed.
There are many types of lightly-doped drain (LDD) transistors presently in use, which are reviewed by A. F. Tasch et al, IEEE Electron Device Letters, Vol. 11, No. 11, pp. 517-519 (1990). In order to reduce the dimensions even further, based on device simulations, it appears that the scaled device must have shallow N.sup.- LDD junctions to overcome charge sharing and doping compensation effects. This permits devices with acceptable short channel threshold and drain induced barrier lowering (DIBL) effects. However, when the peak N.sup.- doping level is increased high enough for acceptable on-resistance, the drain field increases, giving rise to unacceptably high substrate and gate currents.
The so-called GOLD (gate overlapped drain) transistor, described by R. Izawa et al, IEEE Transactions on Electron Devices, Vol. 35, pp. 2088-2093 (1988) overcomes the N.sup.- resistance problem by inducing a channel in the LDD regions with the overlapping gate. This comes at the expense of lower packing density and large Miller capacitance.
Thus, there remains a need for a process for fabricating CMOS transistors having channel lengths down to 0.35 micrometers.